In CMOS device fabrication, several factors that motivate device scaling include shorter channel lengths and the higher speed and reduced power requirements that result from the shorter channel lengths. For example, a ring oscillator based on a 0.18-μm CMOS platform has a gate delay time of more than 20 ps. However, if the channel length is scaled to 0.11 μm, the gate delay time may be reduced to about 15 ps. In addition, using this type of high-speed device in an analog-to-digital converter allows speeds of up to 1 Giga-sample/second.
In 200-mm fabrication, the most advanced process is a 0.18-μm CMOS process, which employs a photolithography tool having a wavelength of 248 nm. This photolithography tool is incapable of printing any 0.11-μm features on a wafer under conventional processing. In order to implement a 0.11-μm process, the fabrication process is required to upgrade to a photolithography tool having a wavelength of 193 nm. However, this type of photolithography tool is extremely expensive, costing in the millions of dollars.